Andy Hall

Andy Hall is a Senior Software Architect at Cadence Design Systems, with over 20 years of EDA experience. His current focus is on high performance and low power Clock Tree Synthesis (CTS) having been a key contributor to the Cadence Clock Concurrent Optimization Technology.

His previous developments include a simulated annealing placement engine and inventing a useful skew scheme for Field Programmable Gate Arrays (FPGAs) at Altera.

Andy has a BSc in Computer Science from UCL and is named on multiple patents.